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Computer Architectures - Combinatorial and Sequential Circuits - Counter register with clear and explicit increment

For this circuit, we shall allow the ld signal to take priority over the incr signal, so that if both signals are 1, we load a new contents from the inputs. We shall also make the cl have the highest priority of all.

 

  cl ld incr i3 i2 i1 i0 o3 o2 o1 o0 | o3' o2' o1' o0'
  ---------------------------------------------------
   0  0   0   -  -  -  - c3 c2 c1 c0 | c3  c2  c1  c0
   0  0   1   -  -  -  -  0  0  0  0 |  0   0   0   1
   0  0   1   -  -  -  -  0  0  0  1 |  0   0   1   0
   0  0   1   -  -  -  -  0  0  1  0 |  0   0   1   1
   0  0   1   -  -  -  -  0  0  1  1 |  0   1   0   0
   0  0   1   -  -  -  -  0  1  0  0 |  0   1   0   1
   0  0   1   -  -  -  -  0  1  0  1 |  0   1   1   0
   0  0   1   -  -  -  -  0  1  1  0 |  0   1   1   1
   0  0   1   -  -  -  -  0  1  1  1 |  1   0   0   0
   0  0   1   -  -  -  -  1  0  0  0 |  1   0   0   1
   0  0   1   -  -  -  -  1  0  0  1 |  1   0   1   0
   0  0   1   -  -  -  -  1  0  1  0 |  1   0   1   1
   0  0   1   -  -  -  -  1  0  1  1 |  1   1   0   0
   0  0   1   -  -  -  -  1  1  0  0 |  1   1   0   1
   0  0   1   -  -  -  -  1  1  0  1 |  1   1   1   0
   0  0   1   -  -  -  -  1  1  1  0 |  1   1   1   1
   0  0   1   -  -  -  -  1  1  1  1 |  0   0   0   0
   0  1   -  c3 c2 c1 c0  -  -  -  - | c3  c2  c1  c0
   1  -   -   -  -  -  -  -  -  -  - |  0   0   0   0

This is exactly the circuit we will use for the program counter (or PC) of our simple example computer, except that the PC in our computer will be 8 bits wide instead of 4.

 


 

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