A counter register with clear is a sequential circuit with n + 2 inputs and n outputs. It differs from an ordinary counter register in that it also has a signal cl for clearing the contents. It is a matter of taste what we want the circuit to do when both the ld and the cl signals are 1. In our application, we want the cl signal to take priority over the ld signal. Here is a state table (abbreviated) for a 4-bit counter register with clear:   ``` cl ld i3 i2 i1 i0 o3 o2 o1 o0 | o3' o2' o1' o0' ---------------------------------------------- 0 0 - - - - 0 0 0 0 | 0 0 0 1 0 0 - - - - 0 0 0 1 | 0 0 1 0 0 0 - - - - 0 0 1 0 | 0 0 1 1 0 0 - - - - 0 0 1 1 | 0 1 0 0 0 0 - - - - 0 1 0 0 | 0 1 0 1 0 0 - - - - 0 1 0 1 | 0 1 1 0 0 0 - - - - 0 1 1 0 | 0 1 1 1 0 0 - - - - 0 1 1 1 | 1 0 0 0 0 0 - - - - 1 0 0 0 | 1 0 0 1 0 0 - - - - 1 0 0 1 | 1 0 1 0 0 0 - - - - 1 0 1 0 | 1 0 1 1 0 0 - - - - 1 0 1 1 | 1 1 0 0 0 0 - - - - 1 1 0 0 | 1 1 0 1 0 0 - - - - 1 1 0 1 | 1 1 1 0 0 0 - - - - 1 1 1 0 | 1 1 1 1 0 0 - - - - 1 1 1 1 | 0 0 0 0 0 1 c3 c2 c1 c0 - - - - | c3 c2 c1 c0 1 - - - - - - - - - | 0 0 0 0 ``` This is exactly the circuit we will use for the micro program counter (or micro PC) of our simple example computer, except that in our example computer, the micro PC will be 6 bits wide instead of 4.