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Computer Architectures - Combinatorial and Sequential Circuits - Counter register with clear

It is a matter of taste what we want the circuit to do when both the ld and the cl signals are 1. In our application, we want the cl signal to take priority over the ld signal.

 

  cl ld i3 i2 i1 i0 o3 o2 o1 o0 | o3' o2' o1' o0'
  ----------------------------------------------
   0  0  -  -  -  -  0  0  0  0 |  0   0   0   1
   0  0  -  -  -  -  0  0  0  1 |  0   0   1   0
   0  0  -  -  -  -  0  0  1  0 |  0   0   1   1
   0  0  -  -  -  -  0  0  1  1 |  0   1   0   0
   0  0  -  -  -  -  0  1  0  0 |  0   1   0   1
   0  0  -  -  -  -  0  1  0  1 |  0   1   1   0
   0  0  -  -  -  -  0  1  1  0 |  0   1   1   1
   0  0  -  -  -  -  0  1  1  1 |  1   0   0   0
   0  0  -  -  -  -  1  0  0  0 |  1   0   0   1
   0  0  -  -  -  -  1  0  0  1 |  1   0   1   0
   0  0  -  -  -  -  1  0  1  0 |  1   0   1   1
   0  0  -  -  -  -  1  0  1  1 |  1   1   0   0
   0  0  -  -  -  -  1  1  0  0 |  1   1   0   1
   0  0  -  -  -  -  1  1  0  1 |  1   1   1   0
   0  0  -  -  -  -  1  1  1  0 |  1   1   1   1
   0  0  -  -  -  -  1  1  1  1 |  0   0   0   0
   0  1 c3 c2 c1 c0  -  -  -  - | c3  c2  c1  c0
   1  -  -  -  -  -  -  -  -  - |  0   0   0   0

This is exactly the circuit we will use for the micro program counter (or micro PC) of our simple example computer, except that in our example computer, the micro PC will be 6 bits wide instead of 4.

 


 

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