A counter register with clear and increment is a sequential circuit with n + 3 inputs and n outputs. It differs from an ordinary counter register with clear in that it also has a signal incr for explicit counting. When the incr signal is 0 the output does not change, and when incr is 1, the circuit works as a counter.

For this circuit, we shall allow the ld signal to take priority over the incr signal, so that if both signals are 1, we load a new contents from the inputs. We shall also make the cl have the highest priority of all.

Here is a state table (abbreviated) for a 4-bit counter register with clear and increment:

  cl ld incr i3 i2 i1 i0 o3 o2 o1 o0 | o3' o2' o1' o0'
  ---------------------------------------------------
   0  0   0   -  -  -  - c3 c2 c1 c0 | c3  c2  c1  c0
   0  0   1   -  -  -  -  0  0  0  0 |  0   0   0   1
   0  0   1   -  -  -  -  0  0  0  1 |  0   0   1   0
   0  0   1   -  -  -  -  0  0  1  0 |  0   0   1   1
   0  0   1   -  -  -  -  0  0  1  1 |  0   1   0   0
   0  0   1   -  -  -  -  0  1  0  0 |  0   1   0   1
   0  0   1   -  -  -  -  0  1  0  1 |  0   1   1   0
   0  0   1   -  -  -  -  0  1  1  0 |  0   1   1   1
   0  0   1   -  -  -  -  0  1  1  1 |  1   0   0   0
   0  0   1   -  -  -  -  1  0  0  0 |  1   0   0   1
   0  0   1   -  -  -  -  1  0  0  1 |  1   0   1   0
   0  0   1   -  -  -  -  1  0  1  0 |  1   0   1   1
   0  0   1   -  -  -  -  1  0  1  1 |  1   1   0   0
   0  0   1   -  -  -  -  1  1  0  0 |  1   1   0   1
   0  0   1   -  -  -  -  1  1  0  1 |  1   1   1   0
   0  0   1   -  -  -  -  1  1  1  0 |  1   1   1   1
   0  0   1   -  -  -  -  1  1  1  1 |  0   0   0   0
   0  1   -  c3 c2 c1 c0  -  -  -  - | c3  c2  c1  c0
   1  -   -   -  -  -  -  -  -  -  - |  0   0   0   0

This is exactly the circuit we will use for the program counter (or PC) of our simple example computer, except that the PC in our computer will be 8 bits wide instead of 4.