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Computer Architectures - Combinatorial and Sequential Circuits - Counter with clear

 

  cl o3 o2 o1 o0 | o3' o2' o1' o0'
  --------------------------------
   0  0  0  0  0 |  0   0   0   1
   0  0  0  0  1 |  0   0   1   0
   0  0  0  1  0 |  0   0   1   1
   0  0  0  1  1 |  0   1   0   0
   0  0  1  0  0 |  0   1   0   1
   0  0  1  0  1 |  0   1   1   0
   0  0  1  1  0 |  0   1   1   1
   0  0  1  1  1 |  1   0   0   0
   0  1  0  0  0 |  1   0   0   1
   0  1  0  0  1 |  1   0   1   0
   0  1  0  1  0 |  1   0   1   1
   0  1  0  1  1 |  1   1   0   0
   0  1  1  0  0 |  1   1   0   1
   0  1  1  0  1 |  1   1   1   0
   0  1  1  1  0 |  1   1   1   1
   0  1  1  1  1 |  0   0   0   0
   1  0  0  0  0 |  0   0   0   0
   1  0  0  0  1 |  0   0   0   0
   1  0  0  1  0 |  0   0   0   0
   1  0  0  1  1 |  0   0   0   0
   1  0  1  0  0 |  0   0   0   0
   1  0  1  0  1 |  0   0   0   0
   1  0  1  1  0 |  0   0   0   0
   1  0  1  1  1 |  0   0   0   0
   1  1  0  0  0 |  0   0   0   0
   1  1  0  0  1 |  0   0   0   0
   1  1  0  1  0 |  0   0   0   0
   1  1  0  1  1 |  0   0   0   0
   1  1  1  0  0 |  0   0   0   0
   1  1  1  0  1 |  0   0   0   0
   1  1  1  1  0 |  0   0   0   0
   1  1  1  1  1 |  0   0   0   0

As you can see, our conter behaves like an ordinary one when the cl signal is 0, and always goes to 0 when the cl signal is 1.

 


 

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